re gulat ing pulse widt h m odulat or block diagram figure 1 block diagram ? 8v to 40v operation ? 5v reference ? reference line and load regulation of 0.4% ? 100hz to 300khz oscillator range ? excellent external sync capability ? dual 50ma o utput transistors ? current limit circuitry ? complete pwm power control circuitry ? single ended or p ush-pull outputs high re liability features followi ng ar e th e hi gh r eliability fe atures of sg1524 : ? available to mil-std-883, ? 1.2.1 ? mil-m38510/12601bea SG1524J-JAN ? msc -a ms level s pr ocessing av ailable this monolithic integrated circuit contains all the control circuitry for a regulating power supply inverter or switching regulator. included in a 16-pin dual-in-line package is the voltage reference, error amplifier, oscillator, pulse width modulator, pulse steering flip-flop, dual alternating output switches and current limiting and shut-down circuitry. this device can be used for switching regulators of either polarity, transformer coupled dc to dc converters, transformerless voltage doublers and polarity converters, as well as other power applications. the sg1524 is specified for operation over the full military ambient temperature range of -55c to +125c, the sg2524 for -25c to +85c, and the sg3524 is designed for commercial applications of 0c to +70c. sg1524/sg2524/sg3524 february 2015 rev. 1.2 1 www.microsemi.com ? 2015 microsemi c orporation features description ? total supply current less than 10ma ? available to dscc - standard microcircuit drawing (smd) downloaded from: http:///
2 oscillator charging current ................................................ 5ma operating junction temperature hermetic (j, l packages) .......................... .... ................... 150 c plastic (n, d packages) ...................................... .... ......... 150 c storage temperature range ................. . ............-65 c to 150 c pb-free / rohs peak package solder reflow temp (40 sec. max. exposure)... 260c (+0, -5) input voltage (+v in ) ............................................................. 42v collector voltage ................................................................ 40v logic inputs ........................................................... -0.3v to 5.5v current limit sense inputs ................................... -0.3v to 0.3v output current (each transistor) .................................... 100ma reference load current .................................................. 50ma input voltage (+v in ) ................................................... collector voltage .......................................................error amp common mode range .......................... current limit sense common mode range ........ output current (each transistor) ............................... reference load current ........................................... oscillator charging current .................................. 8v to 40v0v to 40v 1.8v to 3.4v -0.3v to 0.3v 0 to 50ma0 to 20ma 30 a to 2ma oscillator frequency range .........................oscillator timing resistor (r t ) ........................ oscillator timing capacitor (c t ) ............................ operating ambient temperature range sg1524 .........................................................sg2524 ........................................................... sg3524 ............................................................... 100hz to 300 k hz 1.8 k to 100 k ? 1nf to 1.0 f -55 c to 125 c -25 c to 85 c 0 c to 70 c note 2: range over which the device is functional and parameter limits are guaranteed. (unless otherwise specified, these specifications apply over the operating ambient temperatures for sg1524 with -55 c t a 125 c, sg2524 with -25 c t a 85 c, sg3524 with 0 c t a 70 c, and +v in = 20v. low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)note 3. i l = 0ma 5.00 50 reference section (note 3) t j = 25 c v in = 8v to 40v i l = 0 to 20ma over operating temperature rangeover line, load and temperature v ref = 0v output voltageline regulation load regulation temperature stability (note 7) total output voltage range (note 7) short circuit current min. typ. max. min. typ. max. sg3524 sg1524/ sg 2524 units test conditions parameter 4.804.80 25 5.20 2050 50 5.20 150 4.604.60 25 5.00 50 5.40 3050 50 5.40 150 v mvmv mv v ma thermal resistance- junction to case , jc ............... 30c/w thermal resistance- junction to ambient, ja ........... 80c/w n package: thermal resistance- junction to case , jc ............... 40c/w thermal resistance- junction to ambient, ja ........... 65c/w d package: thermal resistance- junction to case , jc ............... 50c/w thermal resistance- junction to ambient, ja ......... 120c/w l package: thermal resistance- junction to case , jc ........... .... 35c/w thermal resistance- junction to ambient, ja ......... 120c/w no te a. junction temperature calculation: t j = t a + (p d x ja ). note b . the above numbers for jc are maximums for the limiting thermal resistance of the package in a standard mounting configuration. the ja numbers are meant to be guidelines for the thermal performance of the device/pc- board system. all of the above assume no ambient airflow. lead temperature (soldering, 10 seconds).....................300c absolute maximum ratings (note 1) note 1 : values beyond which damage may occur. j package: thermal data recommended operating conditions (note 2) electrical characteristics downloaded from: http:///
3 v in = 40v standby current 0.8 0.50.2 threshold voltage t j = 25 c min t j max 200 190 current limit amplifier section (note 6) sense voltageinput bias current 49 0 45 49 45 p.w.m. comparator (note 4) v comp = 0.5v v comp = 3.6v minimum duty cyclemaximum duty cycle 0 %% error amplifier section (note 5) r s 2 k r l 10m , t j = 25 c v pin 1 - v pin 2 150mv v pin 2 - v pin 1 150mv v cm = 1.8v to 3.4v v in = 8v to 40v t j = 25 c input offset voltageinput bias current input offset current dc open loop gain output low level output high level common mode rejection supply voltage rejection gain-bandwidth product (note 7) 3634 200 3 0.63.2 0.3 oscillator section (note 4) initial accuracyvoltage stability maximum frequency sawtooth peak voltage sawtooth valley voltage clock amplitude clock pulse width min. typ. max. min. typ. max. sg1524/ sg 2524 sg3524 units test conditions parameter t j = 25 c min t j max v in = 8v to 40v r t = 2 k , c t = 1nf v in = 40v v in = 8v k hz k hz% k hz vv v s 4446 1 3.81.2 1.5 40 0.1 400 1 3634 200 3 0.63.2 0.3 4446 1 3.81.2 1.5 40 0.1 400 1 mv a a db vv dbdb mhz 1010 2 0.5 21 0.24.2 2 60 3.8 1 5 10 1 0.5 0.5 1 0.24.2 2 72 3.8 7055 1 210200 180 200 220 200 mv a t j = 25 c shutdown section 1.21.8 0.50.2 0.8 1.2 1.8 vv a vv s s 50 2 0.40.2 50 2 0.40.2 17 17 output section (each transistor) collector leakage currentcollector saturation voltage emitter output voltage collector voltage rise time collector voltage fall time v ce = 40v i c = 50ma i e = 50ma r c = 2 k r c = 2 k power consumption note 4. f osc = 40 k hz (r t = 2.9 k , c t = .01 f) note 5. v cm = 2.5v note 6. v cm = 0v note 7. these parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. 10 7 10 7m a electrical characteristics (continued) downloaded from: http:///
4 oscillator the oscillator in the sg1524 uses an external resistor r t to establish a constant charging current into an external capacitor c t . while this uses more current than a series-connected rc, it provides a linear ramp voltage at c t which is used as a time- dependent reference for the pwm comparator. the charging current is equal to 3.6v/r t , and should be restricted to between 30 a and 2ma. the equivalent range for r t is 100k to 1.8k. the range of values for c t also has limits, as the discharge time of c t determines the pulse width of the oscillator output pulse. the pulse is used (among other things) as a blanking pulse to both outputs to insure that there is no possibility of having both outputs on simultaneously during transitions. this output deadtime relationship is shown in figure 2. a pulse width below 0.35 microseconds may cause failure of the internal flip-flop to toggle. this restricts the minimum value of c t to 1000pf. (note: although the oscillator output is a convenient oscilloscope sync input, the probe capacitance will increase the pulse width and decrease the oscillator frequency slightly.) obviously, the upper limit to the pulse width is determined by the modulation range required in the power supply at the chosen switching frequency. practical values of c t fall between 1000pf and 0.1f, although successful 120 hz oscillators have been implemented with values up to 5f and a series surge limit resistor of 100 ohms. the oscillator frequency is approximately 1/r t ?c t ; where r is in ohms, c is in microfarads, and the frequency is in megahertz. for greater accuracy, the chart in figure 3 may be used for a wide range of operating frequencies. note that for buck regulator topologies, the two outputs can bewire-ored for an effective 0-90% duty cycle range. with this connection, the output frequency is the same as the oscillator frequency. for push-pull applications, the outputs are used separately; the flip-flop limits the duty cycle range at each output to 0-45%, and the effective switching frequency at the trans- former is 1/2 the oscillator frequency. if it is desired to synchronize the sg1524 to an external clock, a positive pulse may be applied to the clock pin. the oscillator should be programmed with r t and c t v alues that cause it to free- run at 90% of the external sync frequency. a sync pulse with a maximum logic 0 of +0.3 volts and a minimum logic 1 of +2.4 volts applied to pin 3 will lock the oscillator to the external source. the minimum sync pulsewidth should be 200 nanoseconds, and the maximum is determined by the required deadtime. the clock pin should never be driven more negative than -0.3 volts, nor more positive than +5.0 volts. the nominal resistance to ground is 3.2 k at the clock pin, 25% over temperature. if two or more sg1524 ' s must be synchronized together, program one master unit with r t and c t for the desired frequency. leave the r t pins on the slaves open, connect the c t pins to the c t of the master, and connect the clock pins to the clock pin of the master. since c t is a high-impedance node, this sync technique works best when all devices are close together. application notes figure 2 output stage deadtime v s . c t figure 3 oscillator frequency v s . r t and c t 1k 2k 5k 10k 20k 50k 100k 200k 500k 1k 2k 5k 10k 20k 50k 100k 500 . 00 1 .002 .005 .01 .02 .05 0.1 0.2 0.5 1 2 5 1 0 20 downloaded from: http:///
5 current limiting the current limiting circuitry of the sg1524 is shown in figure 4 . by matching the base-emitter voltages of q1 and q2, and assuming a negligible voltage drop across r1: c.l. threshold = v be (q1) + i 1 ? r 2 - v be (q2) = i 1 ? r 2 ~ 200 mv although this circuit provides a relatively small threshold with anegligible temperature coefficient, there are some limitations to its use because of its simplicity. the most important of these is the limited common-mode voltage range: 0.3 volts around ground. this requires sensing in the ground or return line of the power supply. also precautions should be taken to not turn on the parasitic substrate diode of the integrated circuit, even under transient conditions. a schottky clamp diode at pin 5 may be required in some configurations to achieve this. a second factor to consider is that the response time is relatively slow. the current limit amplifier is internally compensated by r 1 , c 1 , a nd q1, resulting in a roll-off pole at approximately 300 hz. a third factor to consider is the bias current of the c.l. s ense pins. a constant current of approximately 150 a flows out of pin 4, and a variable current with a range of 0-150 a flows out of pin 5 . as a result, the equivalent source impedance seen by the current sense pins should be less than 50 ohms to keep the threshold error less than 5%. since the gain of this circuit is relatively low (42 db), there is a transition region as the current limit amplifier takes over pulse width control from the error amplifier. for testing purposes, threshold is defined as the input voltage required to get 25% duty cycle (+2 volts at the error amplifier output) with the error amplifier signaling maximum duty cycle. application note: if the current limit function is not used on the sg1524, the common-mode voltage range restriction re - quires both current sense pins to be grounded. in this conventional single-ended regulator circuit, the two out-puts of the sg1524 are connected in parallel for effective 0 - 90% duty-cycle modulation. the use of an output inductor requires and r-c phase compensation network for loop stability. push-pull outputs are used in this transformer-coupled dc-dc regulating converter. note that the oscillator must be set at twice the desired output frequency as the sg1524's internal flip-flop divides the frequency by 2 as it switches the pwm signal from one output to the other. current limiting is done here in the primary so that the pulse width will be reduced should transformer saturation occur. application notes (continued) figure 4 current limiting circuitry of the sg1524 5k 5k 5k 5k 20k 1 k 1 k 1 k 1 k 2k 5k 5k 5k 5k 3k 2k 50k downloaded from: http:///
6 note 1. contact factory for jan product availablity. 2. all packages are viewed from the top. 16-pin ceramic dipj - package v ref +v in e b c b c a e a shutdowncompensation ground osc. output n.i. input ambient temperature range -55 c to 125 c -55 c to 125 c sg1524j - 883b SG1524J-JAN sg1524j -d esc -55 c to 125 c -55 c to 125 c -25 c to 85 c sg1524j sg2524j sg3524j 0 c to 70 c part no. package connection diagram inv. input c t r t +c.l. sense -c.l. sense 23 4 5 6 7 8 1 15 1614 13 10 9 1211 23 4 5 6 7 8 ground osc. output n.i. input inv. input c t r t +c.l. sense -c.l. sense 1 15 1614 13 10 1211 9 v ref +v in e b c b c a e a shutdowncompensation sg2524n -25 c to 85 c sg3524n 0 c to 70 c n package: rohs / pb-free transition dc: 0503*. 100% matte tin lead finish 16-pin plastic dipn - package 16-pin narrow body plastic soicd - package sg2524d -25 c to 85 c sg3524d 0 c to 70 c 20-pin ceramicleadless chip carrier l- package 45 6 7 8 321 9 111213 10 14 15 16 17 18 20 19 -55 c to 125 c sg1524l - 883b sg1524l -55 c to 125 c 11. comp12. shutdown 13. n.c. 14. e a 15. c a 16. n.c.17. c b 18. e b 19. n.c.20. +v in 1. n.c.2. v ref 3. inv. input4. n.i. input 5. osc. output 6. + c.l. sense 7. - c.l. sense 8. r t 9. c t 10. ground rohs / pb-free transition dc:0440 pb-free / rohs 100% matte tin lead finish* *rohs compliant connection diagrams and ordering information (see notes below) 3 . hermetic packages j & l use p b37/sn63 hot solder lead finish, c ontact factory for av ailability of rohs versions. downloaded from: http:///
package outline dimensions package outline dimensions note: dimensions do not include protrusions; these shall not exceed 0.155mm (.006) on any side. lead dimension shall not include solder coverage. figure 5 j 16-pin ceramic dip dim millimeters inches min max min max a - 5.33 - 0.21 0 a1 0.38 - 0.015 - a2 3.30 typ. 0.130 typ. b 0.3 6 0.5 6 0.01 4 0.02 2 b1 1.14 1.78 0.045 0.070 c 0.20 0.3 6 0.008 0.01 4 d 18.67 19.69 0.73 5 0.775 e 2.54 bsc 0.100 bsc e 7.62 8.26 0.300 0.325 e1 6.10 7.11 0.240 0.280 l 2.92 0.381 0.115 0.150 - 15 - 15 note: dimensions do not include protrusions; these shall not exceed 0.155mm (.006) on any side. lead dimension shall not include s older coverage. figure 6 n 16-p in plastic d ual inline package dimensions 7 mi llimeters in ches min max min max a 5.08 0.200 b 0.38 0.51 0.015 0.020 b2 1.04 1.65 0.045 0.065 c 0.20 0.38 0.008 0.015 d 19.30 19.94 0.760 0.785 e 5.59 7.11 0.220 0.280 e 2.54 bsc 0.100 bsc ea 7.37 7.87 0.290 0.310 h 0.63 1.78 0.025 0.070 l 3.18 5.08 0.125 0.20 0 - 15 - 15 q 0.51 1.02 0.020 0.040 d e 9 16 1 8 ea b h b2 c seating plane e q a l dim controlling dimensions are in inches, metric equivalents are shown for genera l information. - - a e1 d e b l e c b1 s eating p lane 1 a2 a1 downloaded from: http:///
package outline dimensions (continued) figure 7 d 16-pin plastic soic d e3 l l2 b1 e b3 a2 a1 a 1 3 8 13 18 h e dim millimeters inches min max min max d/e 8.64 9.14 0.340 0.360 e3 - 8.128 - 0.320 e 1.270 bsc 0.050 bsc b1 0.635 typ 0.025 typ l 1.02 1.52 0.040 0.060 a 1.626 2.286 0.064 0.090 h 1.016 typ 0.040 typ a1 1.372 1.68 0.054 0.066 a2 - 1.168 - 0.046 l2 1.91 2.41 0.075 0.95 b3 0.203r 0.008r note: all exposed metalized area shall be gold plated 60 micro - inch minimum thickness over nickel plated unless otherwise specified in purchase order. figure 8 l 2 0 -p in ceramic lcc package outline dimensions 8 i nches mil limeters min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.25 1.5 2 0.049 0.060 b 0.3 3 0.51 0.01 3 0.020 c 0.19 0.25 0.007 0.010 d 9.78 10.01 0.385 0.394 e 5.79 6.20 0. 228 0.244 e 1. 27 bsc 0. 050 bsc h 3.81 4.01 0.150 0.158 l 0.40 1.27 0.016 0.050 0 8 0 8 *lc 0.10 0.004 * lead coplanarity note:dimensions do not include m old flash or protrus ions; these s hall not exceed 0.155mm ( .006) on any s ide. lead dimension shall not include sold er coverage. d im - - downloaded from: http:///
sg1524.1.2/0 2 .15 microsemi corporate headquarters one enterprise, aliso viejo, ca 92656 usa within the usa : +1 (800) 713-4113 outside the usa : +1 (949) 380-6100 sales : +1 (949) 380-6136 fax : +1 (949) 215-4996 e-mail: sales.support@microsemi.com microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor and system solutions for comm unications, defense & securi ty, aerospace and industrial markets. products include high-performance and radiation-hardened analog mixed-signal integrated circuits, fpgas, socs and asi cs; power management products; timing and synchronization devices and precise time soluti ons, setting the worlds standard for time; voice processing devices; rf solutions; discrete components; security technologies and scalable anti-tamper products; power-over-ethernet ic s and midspans; as well as custom design capabilities and services. microsemi is head quartered in aliso viejo, calif., and has approximately 3,400 employees globally. learn more at www.microsemi.com . ? 2015 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. the products sold hereunder and any other products sold by microsem i have been subject to li mited testing and should not be used in conjunction with missi on-critical equipment or applications. any performance specifications are believed to be reliable but are not verified, and buyer must conduct and complete all performance an d other testing of the products, alone and together with, or installed in, any end-products. buyer shall not rely on any data and performance specifications or para meters provided by micr osemi. it is the buyer's responsibility to independently determine suitability of any products and to test and verify the same. the information provided by microsemi hereunder is provi ded "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the buyer. microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other ip rights, whether with regard to such information itself or anything described by such in formation. information provided in this document is proprietary to microsemi, and microsemi reserves the ri ght to make any changes to the information in this document or to any products and services at any time without notice. downloaded from: http:///
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